ZL30161 - Network Synchronization Clock Translator

Product Overview

Microsemi

Part number	ZL30161
Manufacturer	Microsemi
File Size	871.32 KB
Description	Network Synchronization Clock Translator
Datasheet	ZL30161 Datasheet
Additional preview pages of the ZL30161 datasheet.

All device inputs and outputs are LVCMOS unless it is specifically stated to be differential.

For the I/O column, there are digital inputs (I), digital outputs (O), analog inputs (A-I) and analog outputs (A-O).

Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL).
Programmable DPLL/Numerically Controlled Oscillators (NCO).
Synchronizes to any clock rate from 1 Hz to 750 MHz.
Three programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps rms.
Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates.
Digita.

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Published: Jan 21, 2024 |