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128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
GENERAL DESCRIPTION
The MT28F128J3 is a nonvolatile, electrically block-
can provide data protection when connected to ground.
erasable (Flash), programmable memory containing
This pin also enables program or erase lockout during
134,217,728 bits organized as 16,777,218 bytes (8 bits)
power transition.
or 8,388,608 words (16 bits). This 128Mb device is orga-
Micron’s even-sectored Q-Flash devices offer indi-
nized as one hundred twenty-eight 128KB erase blocks.
vidual block locking that can lock and unlock a block
The MT28F640J3 contains 67,108,864 bits organized
using the sector lock bits command sequence.
as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits).
Status (STS) is a logic signal output that gives an
This 64Mb device is organized as sixty-four 128KB erase
additional indicator of the internal state machine (ISM)
blocks.
activity by providing a hardware signal of both status
Similarly, the MT28F320J3 contains 33,554,432 bits
and status masking. This status indicator minimizes
organized as 4,194,304 bytes (8 bits) or 2,097,152 words
central processing unit (CPU) overhead and system
(16 bits). This 32Mb device is organized as thirty-two
power consumption. In the default mode, STS acts as
128KB erase blocks.
an RY/BY# pin. When LOW, STS indicates that the ISM
These three devices feature in-system block lock-
is performing a block erase, program, or lock bit con-
ing. They also have common flash interface (CFI) that
figuration. When HIGH, STS indicates that the ISM is
permits software algorithms to be used for entire fami-
ready for a new command.
lies of devices. The software is device-independent,
Three chip enable (CE) pins are used for enabling and
JEDEC ID-independent with forward and backward
disabling the device by activating the device’s control
compatibility.
logic, input buffer, decoders, and sense amplifiers.
Additionally, the scalable command set (SCS) al-
BYTE# enables selecting x8 or x16 READs/WRITEs
lows a single, simple software driver in all host systems
to the device. BYTE# at logic LOW selects an 8-bit mode
to work with all SCS-compliant Flash memory devices.
et4U.com The SCS provides the fastest system/device data trans-
with address A0 selecting between the low byte
and the high byte. BYTE# at logic HIGH enables 16-bit DataShee
fer rates and minimizes the device and system-level
operation.
implementation costs.
DataSheet4U.coRmP# is used to reset the device. When the device is
To optimize the processor-memory interface, the
device accommodates VPEN, which is switchable during
disabled and RP# is at VCC, the standby mode is en-
abled. A reset time (tRWH) is required after RP#
block erase, program, or lock bit configuration, or
hardwired to VCC, depending on the application. VPEN is
switches HIGH until outputs are valid. Likewise, the
device has a wake time (tRS) from RP# HIGH until
treated as an input pin to enable erasing, program-
WRITEs to the command user interface (CUI) are rec-
ming, and block locking. When VPEN is lower than the
ognized. When RP# is at GND, it provides write protec-
VCC lockout voltage (VLKO), all program functions are
tion, resets the ISM, and clears the status register.
disabled. Block erase suspend mode enables the user
A variant of the MT28F320J3 also supports the new
to stop block erase to read data from or program data to
security block lock feature for additional code security.
any other blocks. Similarly, program suspend mode
This feature provides an OTP function for locking the
enables the user to suspend programming to read data
top two blocks, the bottom two blocks, or the entire
or execute code from any unsuspended blocks.
device. (Contact factory for availability.)
VPEN serves as an input with 2.7V, 3.3V, or 5V for
application programming. VPEN in this Q-Flash family
DataSheet4U.com
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
DataSheet4 U .com
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
