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MT5C2565 Datasheet Preview

MT5C2565 Datasheet

64K x 4 SRAM

No Preview Available !

SRAM
FEATURES
• High speed: 10, 12, 15, 20, 25 and 35ns
• High-performance, low-power, CMOS double-metal
process
• Single +5V ±10% power supply
• Easy memory expansion with CE and OE options
• All inputs and outputs are TTL-compatible
OPTIONS
• Timing
IOns access
12ns access
15ns access
20ns access
25ns access
35ns access
• Packages
Plastic DIP (300 mil)
Plastic SOJ (300 mil)
MARKING
-10
-12
-15
-20
-25
-35
None
DJ
• 2V data retention
• Lowpower
L
P
• Temperature
Commercial (O°C to +70°C)
Industrial (-40°C to +85°C)
Automotive (-40°C to +125°C)
Extended (-55°C to +125°C)
None
IT
AT
XT
• Part Number Example: MT5C2565DJ-35 P
NOTE: Not all combinations of operating temperature, speed, data retention
and low power are necessarily available. Please contact the factory for availabil-
ity of specific part number combinations.
GENERAL DESCRIPTION
The MT5C2565 is organized as a 65,536 x 4 SRAM using
a four-transistor memory cell with a high-speed, low-power
CMOS process. MicronSRAMs are fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Micron offers chip enable (CE) and output enable (OE) with
this organization. These enhancements can place the out-
puts in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE) and CE inputs are both LOW. Reading is ac-
64Kx 4 SRAM
WITH OUTPUT ENABLE
PIN ASSIGNMENT (Top View)
28-Pin SOJ
(8D-2)
28-Pin DIP
(8A-4)
NC 1
AO 2
Al 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
AS 10
A9 11
CE 12
5E 13
Vss 14
b28 Vee
27 ~ A15
P26 A14
P25 A13
P24 A12
P23 All
P22 Al0
P21 NC
P20 NC
P19 D04
P18 D03
P17 D02
P16 DOl
P15 WE
NC 1 '-/ 28 Vee
AO 2
27 A15
Al 3
26 A14
A2 4
25 A13
A3 5
24 A12
A4 6
23 All
A5 7
22 Al0
A6 8
21 NC
A7 9
20 NC
A8 10
19 DQ4
A9 11
CE 12
DE 13
18 D03
17 D02
16 DOl
Vss 14
15 WE
U1
o<
!:t
en
»JJ
3:
complished when WE remains HIGH and CE and OE go
LOW. The device offers a reduced power standby mode
when disabled. This allows system designers to meet low
standby power requirements.
The "P" version provides a reduction in both operating
current (Icc) and TTL standby current (15B1). The latter is
achieved through the use ofgated inputs on the WE, OE and
address lines, which also facilitates the design of battery
backed systems. That is, the gated inputs simplify the
design effort and circuitry required to protect against inad-
vertent battery current drain during power-down, when
inputs may be at undefined levels.
All devices operate from a single +5V power supply and
all inputs and outputs are fully Tn-compatible.
MT5C2565
REV. 12193
1-91
Micron Semiconductor, Inc., reS9N&S the right to change products or specifications without notice.
©1993, Micron Semicol'lduc!or, Inc.




Micron

MT5C2565 Datasheet Preview

MT5C2565 Datasheet

64K x 4 SRAM

No Preview Available !

CJ1
FUNCTIONAL BLOCK DIAGRAM
Vee GND
<
0
--Ci A
en A
--::a
--ls>: A
A
--A
--A
--A
----A
~~
a:
UJ
0
0
() 262,144-BIT
UJ
0
MEMORY ARRAY
S
0a:
(LSB)
...J
0a:
Iz-
0
()
0
~
COLUMN DECODER
(LSB)
POWER
t t t t t t t t DOWN
AAAAAAAA
DQ4
DQ1
CE
OE
WE
MT5C2565
REV. 12/93
TRUTH TABLE
MODE
1lt cr we- DO
POWER
STANDBY
X H X HIGH-Z STANDBY
READ
L LH
Q ACTIVE
NOT SELECTED H L H HIGH-Z ACTIVE
WRITE
XL L
D ACTIVE
1-92
Micron SemIconductor, Inc., reserves the right to change products or specifications without notice.
©1993, Micron Semiconductor, Inc.


Part Number MT5C2565
Description 64K x 4 SRAM
Maker Micron
PDF Download

MT5C2565 Datasheet PDF






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