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MT5C2561 Datasheet Preview

MT5C2561 Datasheet

256K x 1 SRAM

No Preview Available !

MIC::~ON
1-· r"""'I
SRAM
FEATURES
• High speed: 10, 12, 15,20,25 and 35ns
• High-performance, low-power, CMOS double-metal
process
• Single +5V ±10% power supply
• Easy memory expansion with CE option
• All inputs and outputs are TIL-compatible
OPTIONS
MARKING
• Timing
IOns access
12nsaccess
15ns access
20ns access
25ns access
35ns access
-10
-12
-15
-20
-25
-35
• Packages
Plastic DIP (300 mil)
Plastic SOJ (300 mil)
None
DJ
• 2V data retention
• Lowpower
L
P
• Temperature
Commercial (O°C to -t;70°C)
Industrial (-40°C to +85°C)
Automotive (-40°C to +125°C)
Extended (-55°C to +125°C)
None
IT
AT
XT
• Part Number Example: MT5C2561DJ-15 P
NOTE: Not all combinations of operating temperature, speed, data retention
and lowpower are necessarilyavailable. Pleasecontactthe factoryforavailabil-
ity of specific part number combinations.
MT5C2561
256K x 1 SRAM
-256Kx 1 SRAM
c.n
~--------------------~<O
PIN ASSIGNMENT (Top View)
!:i
en
24-Pin DIP
(SA-3)
~.
AIJ 1 "-' 24 Vee
Al 2
23 A17
s:
AS 3
22 A16
AS 4
21 A15
A4 5
20 A14
AS 6
19 A13
AS 7
18 A12
A7 8
17 Al1
All 9
16 Al0
a 10
15 A.
WE 11
Vss 12
l' 0
13 CE
24-Pin SOJ
(SD-1)
AO 1
Al 2
A2 3
AS 4
A4 5
AS 6
A6 7
A7 8
AS 9
Q 10
WE 11
VB. 12
24 bVee
23p A17
P22 A16
P21 A15
P20 A14
P19 A13
P18 A12
P17 All
P16 Al0
P15 A9
14
13
PD
PCE
GENERAL DESCRIPTION
The MT5C2561 is organized as a 262,144 x 1 SRAM using
afour-transistormemorycellwithahigh-speed,low-power
CMOSprocess. MicronSRAMsare fabricated using double-
layer metal, double-layer polysilicon technology.
Forflexibilityinhigh-speedmemory applications,Micron
offers chip enable (C13) with all organizations. This
enhancement can place the outputs in High-Z for
additionalflexibility insystem design. Thex1 configuration
features separate data input and output.
Writing to these devices is accomplished when write
enable (WE) and CEinputs are both LOW. Reading is
accomplished when WE remains HIGH and CE goes LOW.
The device offers a reduced power standby mode when
disabled. This allows system designers to meet low standby
power requirements.
The "P" version prOVides a reduction in both operating
current (Icc) and TTL standby current (ISB!). The latter is
achieved through the use <>f gated inputs on the WE and
address. lines, which also facilitates the design of battery
backed systems. That is, the gated inputs simplify the
.design effort and circuitry requiredtoprotect against inad-
vertent battery current drain during power-down, when
inputs may be at undefined levels.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL-compatible.
MT5C2561
REV. 12/93
1-21
Micron SemlconductOr,lnc., reserves the right to changeproducts or specifications without notice.
01993, Micron SemIconduc1or, Inc.




Micron

MT5C2561 Datasheet Preview

MT5C2561 Datasheet

256K x 1 SRAM

No Preview Available !

MIC:RON
1-· , , '"'''' ,
c.n
<
0
Ci
en A _
:::0 A _
»s:: A _
A_
A_
A_
A_
a:
W
0
0
()
w
0
s:
0a:
A_
(LSB)
FUNCTIONAL BLOCK DIAGRAM
Vee GND
~~
262,144-BIT
MEMORY ARRAY
...J
0a:
Iz-
0
()
:0:::::
MT5C2561
256K x 1 SRAM
D
Q
CE
COLUMN DECODER
(LSB)
tttttttttt
AAAAAA AAAA
POWER
DOWN
WE
TRUTH TABLE
MODE
STANDBY
READ
WRITE
CE WE
INPUT
H X DON'T CARE
L H DON'T CARE
LL
DATA-IN
OUTPUT
HIGH-Z
Q
HIGH-Z
POWER
STANDBY
ACTIVE
ACTIVE
MT5C2561
REV. 12193
1-22
Micron Semiconductor, Inc., reserves the right to change products or specifications without notic'
©1993, Micron Semiconductor, In


Part Number MT5C2561
Description 256K x 1 SRAM
Maker Micron
PDF Download

MT5C2561 Datasheet PDF






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