SY89874U buffer equivalent, programmable clock divider/fanout buffer.
* Integrated Programmable Clock Divider and 1:2 Fanout Buffer
* Guaranteed AC Performance over Temperature and Voltage: - >2.5 GHz fMAX - <250 ps tr/tf - <15 ps W.
* SONET/SDH Line Cards
* Transponders
* High-End Multiprocessor Sensors
General Description
This low-skew, .
This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622 MHz or higher) CML, LVPECL, LVDS, or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed.
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