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SY89874U - Programmable Clock Divider/Fanout Buffer

General Description

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock.

Key Features

  • Integrated programmable clock divider and 1:2 fanout buffer.
  • Guaranteed AC performance over temperature and voltage:.
  • >2.5GHz fMAX.

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Datasheet Details

Part number SY89874U
Manufacturer Micrel Semiconductor
File Size 692.23 KB
Description Programmable Clock Divider/Fanout Buffer
Datasheet download datasheet SY89874U Datasheet

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Other Datasheets by Micrel Semiconductor

Part Number Description
SY89874AU 2.5GHz Any-In to LVPECL Programmable Clock Divider/Fanout Buffer
SY89871U 2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer
SY89872U IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER
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SY89875U IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SY89874U 2.5GHz, Any Differential, In-to-LVPECL, Programmable Clock Divider/Fanout Buffer with Internal Termination General Description This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight passthrough. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin.