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PL133-37 Datasheet Preview

PL133-37 Datasheet

1:3 Fanout Buffer IC

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PL133-37
Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC
FEATURES
3 LVCMOS Outputs
12mA Output Drive Strength
Input/Output Frequency:
o Reference Clock: 1MHz to 150MHz
Supports LVCMOS or Sine Wave Input Clock
Very Low Jitter and Phase Noise
Low Current Consumption
Single 1.8V, 2.5V, or 3.3V, ±10% Power Supply
Operating Temperature Range
o 0°C to 70°C (Commercial)
o -40°C to 85°C (Industrial)
Available in SOT23-6L GREEN/RoHS Compliant
Packages
DESCRIPTION
The PL133-37 is an advanced fanout buffer design
for high performance, low-power, small form-factor
applications. The PL133-37 accepts a reference
clock input of 1MHz to 150MHz and produces three
outputs of the same frequency. Reference clock in-
puts may be LVCMOS or sine-wave signals (the in-
puts are internally AC-coupled). Offered in a small
3mm x 3mm SOT23, the PL133-37 offers the best
phase noise and jitter performance and lowest power
consumption of any comparable IC.
PACKAGE PIN CONFIGURATION
CLK1 1 6 CLK2
GND 2 5 VDD
FIN 3 4 CLK0
SOT23-6L
BLOCK DIAGRAM
CLK0
FIN CLK1
CLK2
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 02/24/15 Page 1




Micrel

PL133-37 Datasheet Preview

PL133-37 Datasheet

1:3 Fanout Buffer IC

No Preview Available !

PL133-37
Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC
PIN DESCRIPTION
Name
Package Pin #
SOT23-6L
Type
Description
CLK1 1 O Output clock
GND 2 P Ground connection
FIN 3 I Reference clock input
CLK0 4 O Output clock
VDD 5 P Power supply
CLK2 6 O Output clock
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections (looks like ringing).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical value to use is 0.1µF.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
(Typical buffer impedance 20Ω)
50Ω line
To CMOS Input
Series Resistor
Use value to match output buffer impedance to
50Ω trace. Typical value 30Ω
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 02/24/15 Page 2


Part Number PL133-37
Description 1:3 Fanout Buffer IC
Maker Micrel
Total Page 5 Pages
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