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ISPLSI2064 - In-System Programmable High Density PLD

Description

The ispLSI 2064 and 2064A are High Density Programmable Logic Devices.

The devices contain 64 Registers, 64 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP).

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Datasheet Details

Part number ISPLSI2064
Manufacturer Lattice Semiconductor
File Size 212.15 KB
Description In-System Programmable High Density PLD
Datasheet download datasheet ISPLSI2064 Datasheet

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Other Datasheets by Lattice Semiconductor

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ISPLSI2064A In-System Programmable High Density PLD
ispLSI2064E In-System Programmable SuperFAST High Density PLD
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LeadFree Package Options Available! ispLSI® 2064/A In-System Programmable High Density PLD USE ispLSI 2064E FOR NEW Features • ENHANCEMENTS — ispLSI 2064A is Fully Form and Function Compatible to the ispLSI 2064, with Identical Timing Specifcations and Packaging — ispLSI 2064A is Built on an Advanced 0.35 Micron E2CMOS® Technology • HIGH DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.
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