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ISPCLOCK5500 Datasheet Preview

ISPCLOCK5500 Datasheet

In-System Programmable Zero-Delay

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ispClock5300S Family
In-System Programmable, Zero-Delay
Universal Fan-Out Buffer, Single-Ended
October 2007
Preliminary Data Sheet DS1010
Features
Four Operating Configurations
• Zero delay buffer
• Zero delay and non-zero delay buffer
• Dual non-zero delay buffer
• Non-zero delay buffer with output divider
8MHz to 267MHz Input/Output Operation
Low Output to Output Skew (<100ps)
Low Jitter Peak-to-Peak (< 70 ps)
Up to 20 Programmable Fan-out Buffers
• Programmable single-ended output standards
and individual enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
Fully Integrated High-Performance PLL
• Programmable lock detect
• Three “Power of 2” output dividers (5-bit)
• Programmable on-chip loop filter
• Compatible with spread spectrum clocks
• Internal/external feedback
Precision Programmable Phase Adjustment
www.DataSh(eSekt4eUw.co)mPer Output
• 8 settings; minimum step size 156ps
- Locked to VCO frequency
• Up to +/- 5ns skew range
• Coarse and fine adjustment modes
Up to Three Clock Frequency Domains
Flexible Clock Reference and External
Feedback Inputs
• Programmable single-ended or differential input
reference standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL, Differential HSTL, Differential
SSTL
• Clock A/B selection multiplexer
• Programmable Feedback Standards
- LVTTL, LVCMOS, SSTL, HSTL
• Programmable termination
All Inputs and Outputs are Hot Socket
Compliant
Full JTAG Boundary Scan Test In-System
Programming Support
Exceptional Power Supply Noise Immunity
Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
48-pin and 64-pin TQFP Packages
Applications
• Circuit board common clock distribution
• PLL-based frequency generation
• High fan-out clock buffer
• Zero-delay clock buffer
ispClock5300S Family Functional Diagram
LOCK
PLL_ BYPASS
REFA /
REFP
REFB /
REFN
REFSEL
FBK
+
0
1
PHASE
FREQ.
DETECT
LOOP
FILTER
VCO
OUTPUT
DIVIDERS
1 V0
0 5-Bit
SKEW
OUTPUT
CONTROL DRIVERS
OUTPUT 1
V1
5-bit
V2
5-bit
OUTPUT
ROUTING
MATRIX
OUTPUT N
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1010_01.4




Lattice Semiconductor

ISPCLOCK5500 Datasheet Preview

ISPCLOCK5500 Datasheet

In-System Programmable Zero-Delay

No Preview Available !

Lattice Semiconductor
ispClock5300S Family Data Sheet
General Description
The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution
applications. The ispClock5312S, the first member of the ispClock5300S family, provides up to 12 single-ended
ultra low skew outputs. Each pair of outputs may be independently configured to support separate I/O standards
(LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen-
dent programmable control of termination, slew-rate, and timing skew. All configuration information is stored on-
chip in non-volatile E2CMOS® memory.
The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the
on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three
frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32).
The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing
matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output.
The ispClock5300S device can be configured to operate in four modes: zero delay buffer mode, dual non-zero
delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay
buffer mode.
The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the
ispClock5300S device family.
Table 1. ispClock5300S Family
Device
ispClock5320S
ispClock5316S
ispClock5312S
ispClock5308S
ispClock5304S
Number of Programmable
Clock Inputs
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
Number of Programmable
Single-Ended Outputs
20
16
12
8
4
Figure 1. ispClock5304S Functional Block Diagram
www.DataSheet4U.com
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
REFSEL
+
0
1
LOCK
RESET
LOCK
DETECT
PHASE
DETECT
LOOP
FILTER
VCO
FBK
VTT_FBK
PLL_ BYPASS OEX OEY
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
SKEW
OUTPUT
CONTROL DRIVERS
OUTPUT
DIVIDERS
1 V0
0 5-bit
BANK_0A
BANK_0B
BANK_1A
V1 BANK_1B
5-bit
SKEW
OUTPUT
V2 CONTROL DRIVERS
5-bit
JTAG INTERFACE
TDI TMS TCK TDO
2


Part Number ISPCLOCK5500
Description In-System Programmable Zero-Delay
Maker Lattice Semiconductor
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