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ISPCLOCK5520 - In-System Programmable Zero-Delay

Download the ISPCLOCK5520 datasheet PDF. This datasheet also covers the ISPCLOCK5300S variant, as both devices belong to the same in-system programmable zero-delay family and are provided as variant models within a single manufacturer datasheet.

General Description

The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications.

The ispClock5312S, the first member of the ispClock5300S family, provides up to 12 single-ended ultra low skew outputs.

Key Features

  • Four Operating Configurations.
  • Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divider.
  • Up to +/- 5ns skew range.
  • Coarse and fine adjustment modes.
  • Up to Three Clock Frequency Domains.
  • Flexible Clock Reference and External Feedback Inputs.
  • Programmable single-ended or differential input reference standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL,.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ISPCLOCK5300S_LatticeSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ISPCLOCK5520
Manufacturer Lattice Semiconductor
File Size 1.28 MB
Description In-System Programmable Zero-Delay
Datasheet download datasheet ISPCLOCK5520 Datasheet

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Other Datasheets by Lattice Semiconductor

Part Number Description
ISPCLOCK5500 In-System Programmable Zero-Delay
ISPCLOCK5510 In-System Programmable Zero-Delay
ISPCLOCK5300S In-System Programmable Zero-Delay
ISPCLOCK5304S In-System Programmable Zero-Delay
ISPCLOCK5308S In-System Programmable Zero-Delay

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ispClock 5300S Family ™ In-System Programmable, Zero-Delay Universal Fan-Out Buffer, Single-Ended October 2007 Preliminary Data Sheet DS1010 Features ■ Four Operating Configurations • • • • Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divider • Up to +/- 5ns skew range • Coarse and fine adjustment modes ■ Up to Three Clock Frequency Domains ■ Flexible Clock Reference and External Feedback Inputs • Programmable single-ended or differential input reference standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL • Clock A/B selection multiplexer • Programmable Feedback Standards - LVTTL, LVCMOS, SSTL, HSTL • Programmable termination ■ 8MHz to 267MHz Input/Output Operation ■ Low Output t