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Intersil Electronic Components Datasheet

CS82C89 Datasheet

CMOS Bus Arbiter

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82C89
March 1997
CMOS Bus Arbiter
Features
Description
• Pin Compatible with Bipolar 8289
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
• Provides Multi-Master System Bus Control and
Arbitration
• Provides Simple Interface with 82C88/8288 Bus
Controller
• Synchronizes 80C86/8086, 80C88/8088 Processors
with Multi-Master Bus
• Bipolar Drive Capability
• Four Operating Modes for Flexible System Configura-
tion
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .1mA/MHz (Max)
• Operating Temperature Ranges
- C82C89 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C89 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C89 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C89 Bus Arbiter is manufactured using a self-
aligned silicon gate CMOS process (Scaled SAJI IV). This cir-
cuit, along with the 82C88 bus controller, provides full bus arbi-
tration and control for multi-processor systems. The 82C89 is
typically used in medium to large 80C86 or 80C88 systems
where access to the bus by several processors must be coordi-
nated. The 82C89 also provides high output current and capac-
itive drive to eliminate the need for additional bus buffering.
Static CMOS circuit design insures low operating power. The
advanced Intersil SAJI CMOS process results in perfor-
mance equal to or greater than existing equivalent products
at a significant power savings.
Ordering Information
PART NUMBER
CP82C89
IP82C89
CS82C89
IS82C89
CD82C89
ID82C89
MD82C89/B
5962-8552801RA
MR82C89/B
5962-85528012A
PACKAGE
20 Ld PDIP
20 Ld PLCC
20 Ld
CERDIP
SMD#
20 Pad
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
PKG.
NO.
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
-55oC to +125oC J20.A
J20.A
Pinouts
82C89 (CERDIP)
TOP VIEW
S2 1
IOB 2
SYSB/RESB 3
RESB 4
BCLK 5
INIT 6
BREQ 7
BPRO 8
BPRN 9
GND 10
20 VCC
19 S1
18 S0
17 CLK
16 LOCK
15 CRQLCK
14 ANYRQST
13 AEN
12 CBRQ
11 BUSY
82C89 (PLCC, CLCC)
TOP VIEW
3 2 1 20 19
RESB 4
BCLK 5
INIT 6
18 S0
17 CLK
16 LOCK
BREQ 7
BPRO 8
15 CRQLCK
14 ANYRQST
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-343
File Number 2980.1


Intersil Electronic Components Datasheet

CS82C89 Datasheet

CMOS Bus Arbiter

No Preview Available !

Functional Diagram
82C89
80C86/
80C88
STATUS
S2
S1
S0
CONTROL/
STRAPPING
OPTIONS
LOCK
CLK
CRQLCK
RESB
ANYRQST
IOB
ARBITRATION
STATUS
DECODER
CONTROL
+5V
MULTIBUS
INTERFACE
INIT
BCLK
BREQ
BPRN
BPRO
BUSY
CBRQ
MULTIBUSTM
COMMAND
SIGNALS
LOCAL
BUS
INTERFACE
AEN
SYSB/
RESB
SYSTEM
SIGNALS
GND
MULTIBUSTM IS AN INTEL CORP. TRADEMARK
Pin Description
PIN
SYMBOL
VCC
NUMBER
20
GND
S0, S1, S2
10
1, 18-19
CLK 17
TYPE
DESCRIPTION
VCC: The +5V Power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for
decoupling.
GROUND.
I STATUS INPUT PINS: The status input pins from an 80C86, 80C88 or 8089 processor. The
82C89 decodes these pins to initiate bus request and surrender actions. (See Table 1).
I CLOCK: From the 82C84A or 82C85 clock chip and serves to establish when bus arbiter actions
are initiated.
LOCK
CRQLCK
RESB
16
15
4
ANYRQST
14
I LOCK: A processor generated signal which when activated (low) prevents the arbiter from surren-
dering the multi-master system bus to any other bus arbiter, regardless of its priority.
I COMMON REQUEST LOCK: An active low signal which prevents the arbiter from surrendering the
multi-master system bus to any other bus arbiter requesting the bus through the CBRQ input pin.
I RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a
multi-master system bus and a Resident Bus. Strapped high, the multi-master system bus is re-
quested or surrendered as a function of the SYSB/RESB input pin. Strapped low, the SYSB/RESB
input is ignored.
I ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered
to a lower priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter
requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible).
When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Informa-
tion. If ANYRQST is strapped high and CBRQ is activated, the bus is surrendered at the end of
the present bus cycle. Strapping CBRQ low and ANYRQST high forces the 82C89 arbiter to sur-
render the multi-master system bus after each transfer cycle. Note that when surrender occurs
BREQ is driven false (high).
4-344


Part Number CS82C89
Description CMOS Bus Arbiter
Maker Intersil Corporation
Total Page 15 Pages
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