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IS61VF10018 - 512K x 32 Synchronous Flow-through Static RAM

Download the IS61VF10018 datasheet PDF. This datasheet also covers the IS61VF51232 variant, as both devices belong to the same 512k x 32 synchronous flow-through static ram family and are provided as variant models within a single manufacturer datasheet.

Description

are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.

Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Linear burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • JEDEC 100-Pin TQFP and 119-pin PBGA package.
  • Single +2.5V, ±5% operation.
  • Auto Power-down during deselect.
  • Sing.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61VF51232_IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61VF51232 IS61VF51236 IS61VF10018 512K x 32, 512K x 36, 1024K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM ISSI ® ADVANCE INFORMATION October 2001 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Linear burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP and 119-pin PBGA package • Single +2.
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