IS61DDPB251236A sram equivalent, 18mb ddr-iip(burst 2) cio synchronous sram.
DESCRIPTION
* 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Common I/O read and write ports.
where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.
* 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with self-timed late write operation.
* Double Data Rate (D.
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 509.49KB)