IS43R32800B information equivalent, 256mb ddr synchronous dram preliminary information.
* Vdd/Vddq=2.5V+0.2V (-5, -6, -75)
* Double data rate architecture; two data transfers per clock cycle
* Bidirectional, data strobe (DQS) is transmitted/ r.
IS43R32800B is a 4-bank x 2,097,152-word x32bit Double Data Rate Synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output dat.
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