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IS67WVC2M16ECLL - 32Mb Async/Page/Burst CellularRAM

Download the IS67WVC2M16ECLL datasheet PDF. This datasheet also covers the IS66WVC2M16EALL variant, as both devices belong to the same 32mb async/page/burst cellularram family and are provided as variant models within a single manufacturer datasheet.

Description

CellularRAMâ„¢ (Trademark of MicronTechnology Inc.) products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications.

The 32Mb DRAM core device is organized as 2 Meg x 16 bits.

Features

  • Single device supports asynchronous , page, and burst operation.
  • Mixed Mode supports asynchronous write and synchronous read operation.
  • Dual voltage rails for optional performance.
  • ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V.
  • CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V.
  • Asynchronous mode read access : 70ns Interpage Read access : 70ns Intrapage Read access : 25ns.
  • Burst mode for Read and Write operation.
  • 4, 8, 16,32 or Continuous.
  • Low Power Consumption.
  • Async.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS66WVC2M16EALL-ISSI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS66WVC2M16EALL/CLL IS67WVC2M16EALL/CLL 32Mb Async/Page/Burst CellularRAM 1.5 Overview The IS66WVC2M16EALL/CLL is an integrated memory device containing 32Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device includes several power saving modes : Reduced Array Refresh mode where data is retained in a portion of the array and Temperature Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a standard asynchronous mode and high performance burst mode. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
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