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IS61QDPB21M36A - 36Mb QUADP (Burst 2) Synchronous SRAM

Download the IS61QDPB21M36A datasheet PDF. This datasheet also covers the IS61QDPB22M18A variant, as both devices belong to the same 36mb quadp (burst 2) synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

devices.

need for high-speed bus turnaround.

operations are self-timed.

Features

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.5 Cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and cont.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDPB22M18A-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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IS61C256 32K x 8 Low Voltage CMOS STATIC RAM Integrated Silicon Solution
IS61C25616 256K x 8 High Speed CMOS STATIC RAM Integrated Silicon Solution
IS61C25616AL 256K x 16 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDPB21M36A1 36Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB21M36A2 36Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB21M18A 18Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB21M18A1 18Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB21M18A2 18Mb QUADP (Burst 2) Synchronous SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) DECEMBER 2014 FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
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