IS61QDP2B41M18A2 sram equivalent, 18mb quadp (burst 4) synchronous sram.
DESCRIPTION
* 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data
valid window.
* Separate independent read and write.
where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.
* 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data
valid window.
* Separate independent read and write ports with concurrent read and write operations.
* Synchronous pipeline read with late w.
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