IS61QDP2B41M18C2
FEATURES
DESCRIPTION
- 1Mx36 and 2Mx18 configuration available.
- On-chip Delay-Locked Loop (DLL) for wide data valid window.
- Separate independent read and write ports with concurrent read and write operations.
- Synchronous pipeline read with late write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- 2.0 cycle read latency.
- Fixed 4-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only.
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
- Data Valid Pin (QVLD).
- +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
- HSTL input and output interface.
- Registered addresses, write and read controls, byte writes, data in, and data outputs.
- Full data coherency.
- Boundary scan using limited set of JTAG 1149.1 functions.
- Byte write capability.
- Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body...
