Download the IS61QDP2B41M18C2 datasheet PDF.
This datasheet also covers the IS61QDP2B41M18C variant, as both devices belong to the same 18mb quadp synchronous sram family and are provided as variant models within a single manufacturer datasheet.
General Description
1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Full PDF Text Transcription for IS61QDP2B41M18C2 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
IS61QDP2B41M18C2. For precise diagrams, and layout, please refer to the original PDF.
IS61QDP2B41M18C/C1/C2 IS61QDP2B451236C/C1/C2 1Mx18, 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.0 Cycle Read Latency) APRIL 2016 FEATURES DESCRIPTION 1Mx36 and 2Mx...
View more extracted text
.0 Cycle Read Latency) APRIL 2016 FEATURES DESCRIPTION 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data
IS61QDP2B41M18C2 Datasheet
