IS61NVP10018 Datasheet | ISSI

IS61NVP51236 IS61NVP10018 512K x 36 and 1M x 18 PIPELINE 'NO WAIT' STATE BUS SRAM Features - 100 percent bus utilization - No wait cycles between Read and Write - Internal self-timed write cycle .. - Individual Byte Write Control - Single R/W (Read/Write) control pin - Clock controlled, registered address, data and control - Interleaved or linear burst sequence control using MODE input - Three chip enables for simple depth expansion and address pipelining for TQFP - Power Down mode - mon data inputs and data outputs - CKE pin to enable clock and suspend operation - JEDEC 100-pin TQFP, 119 PBGA package - VDD +2.5V power supply (± 5%) - VDDQ: 2.5V I/O Supply Voltage - Industrial temperature available ISSI DESCRIPTION ® PRELIMINARY INFORMATION SEPTEMBER 2002 The 18 Meg 'NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and munications customers. They are organized as 524, 288 words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes...