Description
The device has 4352-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4352-byte increments.
The Erase operation is implemented in a single block unit (256Kbytes + 16Kbytes).
Features
- Flexible & Efficient Memory Architecture
- Memory Cell: 1bit/Memory Cell - Organization: 512Mb x8, 256Mb x16 - Page Size for x8: (4K + 256) Bytes - Page Size for x16: (2K + 128) words - Block Size for x8: 64x (4K + 256) Bytes - Block Size for x16: 64x (2K + 128) words - Number of Plane = 1 - Number of Block per Die (LUN) = 2048.
- ONFI 1.0 compliant.
- Highest performance - Read Performance: - Random Read: 25us (Max. ) - Serial Access: 25ns (Max. ) - Write Performance: - Pr.