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IDT71V35761S - 3.3V Synchronous SRAMs

Download the IDT71V35761S datasheet PDF. This datasheet also covers the IDT71V35761SA variant, as both devices belong to the same 3.3v synchronous srams family and are provided as variant models within a single manufacturer datasheet.

Features

  • 128K x 36 memory configurations.
  • Supports high system speed: Commercial:.
  • 200MHz 3.1ns clock access time Commercial and Industrial:.
  • 183MHz 3.3ns clock access time.
  • 166MHz 3.5ns clock access time.
  • LBO input selects interleaved or linear burst mode.
  • 3.3V core power supply Functional Block Diagram LBO ADV CLK ADSC ADSP.
  • Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx).
  • Power down control.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT71V35761SA-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71V35761S
Manufacturer IDT
File Size 818.92 KB
Description 3.3V Synchronous SRAMs
Datasheet download datasheet IDT71V35761S Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
128K x 36 3.3V Synchronous SRAMs IDT71V35761S/SA 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Features ◆ 128K x 36 memory configurations ◆ Supports high system speed: Commercial: – 200MHz 3.1ns clock access time Commercial and Industrial: – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ 3.3V core power supply Functional Block Diagram LBO ADV CLK ADSC ADSP ◆ Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) ◆ Power down controlled by ZZ input ◆ 3.3V I/O ◆ Optional - Boundary Scan JTAG Interface (IEEE 1149.
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