IDT70V631S Datasheet, IDT

*
*
*
*
*
*
* Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility S.

results in full-speed, error-free operation without the need for additional discrete logic. This device provides two ind.

address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a.