8T74S208 buffer equivalent, 2.5v differential lvds clock divider and fanout buffer.
* One differential input reference clock
* Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
* Integrated input termina.
demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the.
The 8T74S208 is a high-performance differential LVDS clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T74S208 is characterized to operate from a 2.5V .
Image gallery
TAGS
Download