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HYMP125P72CP4-S5 Datasheet

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Hynix Semiconductor · HYMP125P72CP4-S5 File Size : 256.88KB · 2 hits

Features and Benefits


• JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination)



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HYMP125P72CP4-S5 HYMP125P72CP4-S5 HYMP125P72CP4-S5
TAGS
Registered
DDR2
SDRAM
DIMMs
1Gb
HYMP125P72CP4-S5
HYMP125P72CP4-S6
HYMP125P72CP4-C4
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