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HY5S7B6ALFP-6 - 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

General Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

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Datasheet Details

Part number HY5S7B6ALFP-6
Manufacturer SK Hynix
File Size 656.38 KB
Description 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O
Datasheet download datasheet HY5S7B6ALFP-6 Datasheet

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Other Datasheets by SK Hynix

Part Number Description
HY5S7B6ALFP-H 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O
HY5S7B6ALFP-S 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O
HY5S7B6LF-H 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O
HY5S7B6LF-S 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O
HY5S7B6LFP-H 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 1.1 Initial Draft Inserted 166MHz Product Release Insert (Page10) DPD specification [IDD7 : 10uA min] History Draft Date Aug. 2006 Sep. 2006 May. 2007 July. 2007 Remark Preliminary Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.1 / July. 2007 1 512Mbit (32Mx16bit) Mobile SDR Memory HY5S7B6ALF(P) Series DESCRIPTION The Hynix HY5S7B6ALF(P) is suited for non-PC application which use the batteries such as PDAs, 2.