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HY5S7B6LF-H - 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

Description

and Figures Final Version History Draft Date Oct.

2004 May.

2005 Aug.

Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

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Datasheet Details

Part number HY5S7B6LF-H
Manufacturer SK Hynix
File Size 709.96 KB
Description 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O
Datasheet download datasheet HY5S7B6LF-H Datasheet

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Full PDF Text Transcription

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512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 Initial Draft Package size (10 x 13 [mm2]) Defined DC Chatacteristics (Page 10 ~ 11) Modified Address # in Ball Description and Figures Final Version History Draft Date Oct. 2004 May. 2005 Aug. 2006 Aug. 2006 Jan. 2007 Remark Preliminary Preliminary Preliminary Preliminary www.DataSheet4U.com This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Jan.
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