HY5S5B6GLF-6E Datasheet, Hynix Semiconductor

* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)
*
* MULTIBANK OPERATIO.

which requires large memory density and high bandwidth. It is organized as 4banks of 4,194,304x16. Mobile SDRAM is a typ.

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Apr. 2006 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6GLF(P)-xE Series 11 Document Title .