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256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
Specification of 256M (16Mx16bit) Mobile SDRAM
Memory Cell Array
- Organized as 4banks of 4,194,304 x16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Apr. 2006 1
256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6GLF(P)-xE Series
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Document Title
4Bank x 4M x 16bits Synchronous DRAM
Revision History
Revision No. 0.1 Initial Draft 1. Changed 166MHz IDD1 : 60mA --> 75mA 133MHz IDD1 : 55mA --> 65mA 105MHz IDD1 : 50mA --> 55mA 2. Remove CL2 operation (Page 13 to 14) 1. Release History Draft Date Feb. 2006 Remark Preliminary
0.2
Mar. 2006
Preliminary
1.0
Apr. 2006
Final
Rev 1.