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HY5S5B6ELF-SE - 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O

Download the HY5S5B6ELF-SE datasheet PDF. This datasheet also covers the HY5S5B6ELF-HE variant, as both devices belong to the same 256mbit mobile sdr sdrams based on 4m x 4bank x16 i/o family and are provided as variant models within a single manufacturer datasheet.

General Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • Standard SDRAM Protocol.
  • Programmable CAS latency of 1, 2 or 3 -25oC ~ 85oC Operation Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead) Internal 4bank operation Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O power Low Power Features PASR(Partial Array Self Refresh) Auto TCSR (Temperature Compensated Self Refresh) DS (Drive Strength) Deep Power Down Mode.
  • - HY5S5B6ELFP : Lead Free.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HY5S5B6ELF-HE_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HY5S5B6ELF-SE
Manufacturer SK Hynix
File Size 241.92 KB
Description 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
Datasheet download datasheet HY5S5B6ELF-SE Datasheet

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Other Datasheets by SK Hynix

Part Number Description
HY5S5B6ELF-HE 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
HY5S5B6ELFP-HE 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
HY5S5B6ELFP-SE 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
HY5S5B6GLF-6 256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF-6E 256Mbit (16Mx16bit) Mobile SDR Memory

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O Document Title 4Bank x 4M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 1.0 Initial Draft Modification of IDD Current Modification of IDD3P & IDD3PS IDD3P / IDD3PS : 3mA / 2mA --> 5mA / 5mA Final revision History Draft Date Aug. 2004 Oct. 2004 Jan. 2005 Jul. 2005 Remark Preliminary Preliminary Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Jul. 2005 1 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series DESCRIPTION The Hynix Low Power SDRAM(Mobile SDR) is suited for non-PC application which use the batteries such as PDAs, 2.