HY5S5B2BLF-SE sdram equivalent, 256m (8mx32bit) mobile sdram.
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Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)
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MULTIBANK OPERATIO.
which requires large memory density and high bandwidth. It is organized as 4banks of 2,097,152 x32. Mobile SDRAM is a ty.
and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Apr. 2006 1
256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2BLF(P) Series
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4Ban.
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