HY5RS123235FP-14 Datasheet | SK Hynix

HY5RS123235FP 512M (16Mx32) GDDR3 SDRAM HY5RS123235FP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3 / Feb. 2006 1 HY5RS123235FP Revision History Revision No. 0.1 0.2 History Defined target spec. Page 11) Add Cas Latency 11 Page 14) Write Latency definitions Page15) DI, WR_A, AL definitions Page47) Table18 typo corrected Page48) Table19 renewered Page50) note 46 added Page4) Ballout configurations correct Appendix C) BST function description - Non-Consectutive Read to Write timing clarifications - Read to Precharge timing Clarifications - Modified the pin descriptions and added mand description for BST - Added the LP mode feature for EMRS -Added the Lead free package part number and Package dimension page Draft Date Mar. 2004 JULY.2004 CL WL DI/WR_A/AL Speed BIN Several Parameters t RPRE A3/A8/A9/A10 Page28 page41 Page23 Page4,6,21 Page15,16 Jan.31,2005 Page3,56 Remark 0.3 0.4 Aug.2004 Sep.24,2004 Nov.8,2004 - Clarified the ODT control and Data terminator disable mand and its duration timing - Modify the Data termination disable mode note of EMRS - Modified the PIN description of VDDA/ VSSA(K1,12/J1,12) - Changed the t PDIX, from 4t CK to 6t CK - Changed the t XSRD, from 300t Ck to 1000t CK - Added the t CJC definition - IDD spec update - DC spec Update Apr.30,2005 Page 15,20 Page 9 Page 4,7 Page 47 Page 48 page 48 page 46 Table 12 VDD/VDDQ change, 500Mhz Speed Bin Insert, IDD value tuning & typo corrected Jun. 2005 1.2 1.3 VDD/VDDQ Change at 600MHz speed bin to 1.8V from 2.0V 900MHz speed bin insert Nov. 2005 Feb. 2006 Rev. 1.3 / Feb. 2006 HY5RS123235FP DESCRIPTION The Hynix HY5RS123235 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The Hynix HY5RS123235 is internally configured as a eight-bank DRAM. The Hynix HY5RS123235 uses a...