Datasheet4U Logo Datasheet4U.com

HY5DS573222F - 256M(8Mx32) GDDR SDRAM

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • The Hynix HY5DS573222F(P) guarantee until 166MHz speed at DLL_off condition 1.8V VDD and VDDQ wide range max power supply supports All inputs and outputs are compatible with SSTL_2 interface 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS0 ~ DQS3) Data outputs o.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HY5DU281622 4 Banks x 2M x 16Bit Double Data Rate SDRAM Hyundai
HY5DU281622FTP 128Mb DDR SDRAM Hynix
HY5DU281622LT-H 4 Banks x 2M x 16Bit Double Data Rate SDRAM Hyundai
HY5DU281622LT-K 4 Banks x 2M x 16Bit Double Data Rate SDRAM Hyundai
HY5DU281622LT-L 4 Banks x 2M x 16Bit Double Data Rate SDRAM Hyundai

Other Datasheets by SK Hynix

Part Number Description
HY5DS573222FP 256M(8Mx32) GDDR SDRAM
HY5DS283222BF 128M(4Mx32) GDDR SDRAM
HY5DU121622ALT 512Mb DDR SDRAM
HY5DU121622AT 512Mb DDR SDRAM
HY5DU121622B 512 Mb DDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com HY5DS573222F(P) 256M(8Mx32) GDDR SDRAM HY5DS573222F(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Feb. 2005 1 DataSheet 4 U .com www.DataSheet4U.com 1HY5DS573222F(P) Revision History No. 0.1 0.2 0.3 0.4 0.5 1.0 Defined Target Spec. Supports Lead free parts for each speed grade CL, AC parameter, IDD5 change CL, tCK_max, tRAS, tDAL change & Comment of DLL_off condition 1) Changed IDD & VDD_max 2) Changed tRCDWR, tWR, CL, tCK_max at 350Mhz speed bin Version 1.0 Release History Draft Date Mar. 2004 Apr. 2004 Apr. 2004 Jun. 2004 Oct. 2004 Feb. 2005 Remark Rev. 1.0 / Feb. 2005 2 DataSheet 4 U .
Published: |