* On-Chip ECC with virtually zero SER
* Configurable Read Latency (3.0 or 2.0 cycles)
* Simultaneous Read and Write SigmaQuad-IIIe™ Interface
* Separate I.

Symbol Description SA D[35:0] Q[35:0] QVLD[1:0] CK, CK KD[1:0], KD[1:0] CQ[1:0], CQ[1:0] Address—Read Address is registered on ↑CK and Write Address is registered on ↑CK. Write Data—Registered on ↑KD and ↑KD during Write operations. D[17:0]—x18 a.

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