* 2.0 Clock Latency
* On-Chip ECC with virtually zero SER
* Simultaneous Read and Write SigmaQuad™ Interface
* JEDEC-standard pinout and package
* Dua.

where alternating reads and writes are needed. Therefore, the SigmaQuad-II+ ECCRAM interface and truth table are optimiz.

Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0
  –BW3 Synchronous Byte Writes Input Active Low K Input Clock Inp.

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