* IEEE 1149.1 JTAG-compatible Boundary Scan
* 1.8 V +10%/
  –10% core power supply
* 1.8 V I/O supply
* LBO pin for Linear or Interleaved Bur.

* JEDEC-standard 165-bump FP-BGA package
* Pb-Free 165-bump BGA package available Functional Description Applica.

Applications The GS8321V18/32/36E is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds .

GS8321V32E

GS8321V36E

GS8321V36GE

GS8321V18E

GS8321V18GE

GS832118E

GS832118E-V

GS832118GE

GS832118GE-V

GS832132E

GS832132E-V

GS832132GE

GS832132GE-V

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