* For use with GSI FPGA-based Controller IP
* 3.0 Clock Latency
* Simultaneous Read and Write SigmaQuad™ Interface
* JEDEC-standard pinout and package

where alternating reads and writes are needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized.

Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BWn Synchronous Byte Writes Input Active Low K Input Clock Input Active High K Inp.

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