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GS82582D38GE - 288Mb SigmaQuad-II+ SRAM

This page provides the datasheet information for the GS82582D38GE, a member of the GS82582D20GE-550 288Mb SigmaQuad-II+ SRAM family.

Datasheet Summary

Description

Table Symbol Description Type Comments SA Synchronous Address Inputs Input R Synchronous Read Input Acti

Features

  • 2.5 Clock Latency.
  • Simultaneous Read and Write SigmaQuad™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • Burst of 4 Read and Write.
  • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) intputs.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully c.

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Datasheet preview – GS82582D38GE

Datasheet Details

Part number GS82582D38GE
Manufacturer GSI Technology
File Size 312.06 KB
Description 288Mb SigmaQuad-II+ SRAM
Datasheet download datasheet GS82582D38GE Datasheet
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Full PDF Text Transcription

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165-Bump BGA Commercial Temp Industrial Temp GS82582D20/38GE-550/500/450/400 288Mb SigmaQuad-II+ Burst of 4 SRAM 550 MHz–400 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 4 Read and Write • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) intputs • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid Pin (QVLD) Support • IEEE 1149.
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