GS8180QV36BGD sram equivalent, 18mb burst of 2 sigmaquad sram.
* Simultaneous Read and Write SigmaQuad™ Interface
* JEDEC-standard pinout and package
* Dual DoubleData Rate interface
* Byte Write controls sampled at d.
where alternating reads and writes are needed. Therefore, the SigmaQuad SRAM interface and truth table are optimized for.
Table
Symbol
Description
SA Synchronous Address Inputs
NC No Connect
R Synchronous Read
W Synchronous Write
BW0
–BW1
Synchronous Byte Writes
BW2
–BW3
Synchronous Byte Writes
K Input Clock
K Input Clock
C Out.
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