* Simultaneous Read and Write SigmaQuad™ Interface
* JEDEC-standard pinout and package
* Dual DoubleData Rate interface
* Byte Write controls sampled at d.

where alternating reads and writes are needed. Therefore, the SigmaQuad SRAM interface and truth table are optimized for.

Table Symbol Description SA Synchronous Address Inputs NC No Connect R Synchronous Read W Synchronous Write BW0
  –BW1 Synchronous Byte Writes BW2
  –BW3 Synchronous Byte Writes K Input Clock K Input Clock C Out.

GS8180QV18BGD

GS8180QV36BD

GS8180QV36BGD

GS8182D18D

GS8182Q18D

GS8182S08BD

GS8182S08BGD

GS8182S09BD

GS8182S09BGD

GS8182S18BD

GS8182S18BGD

GS8182S18D

GS8182S36BD

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