GS81302T07E sram equivalent, 144mb sigmaddr-ii+ burst of 2 sram.
* 2.0 Clock Latency
* Simultaneous Read and Write SigmaDDR™ Interface
* Common I/O bus
* JEDEC-standard pinout and package
* Double Data Rate interfac.
Therefore, the SigmaDDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs a.
Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R/W
Synchronous Read
Input
High: Read Low: Write
BW0
–BW3
Synchronous Byte Writes
Input Active Low
LD
Synchronous Load Pin
Input Active Low
K.
Image gallery
TAGS
+
Manufacturer
Related datasheet
Download (Size : 219.45KB)