GS81302T06GE sram equivalent, 144mb sigmaddr-ii+ burst of 2 sram.
* 2.5 Clock Latency
* Simultaneous Read and Write SigmaDDRTM Interface
* JEDEC-standard pinout and package
* Double Data Rate interface
* Byte Write c.
Therefore, the SigmaDDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs a.
Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R/W
Synchronous Read/Write
Input
High: Read Low: Write
BW0
–BW3
Synchronous Byte Writes
Input Active Low
LD
Synchronous Load Pin
Input Active .
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