To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to: http://freescale.com/
A full list of family members and options is included in the appendices.
The following revision history table summarizes changes contained in this document.
This document contains information for all constituent modules, with the exception of the S12X CPU. For
S12X CPU information please refer to the CPU S12 Reference Manual Version 2 .
VREG, NVM electrical parameter updates
Use of external regulator now prohibited
Corrected package option code. Added dataﬂash to derivative table.
Included revision history in module sections
Removed internal text
NVM timing parameters, PLL parameters. Minor typo corrections.
NVM timing parameters and EEE description updated.
EBI/NVM/IDD parameter updates
Partnumber coding explanation updated in Appendix F
Ex256 memory map correction
ATD/PLL electricals updated
Revised FTM section
Version ID added to Part ID section
EPROT/FPROT conﬁguration ﬁeld locations changed !!
Various electricals updated following characterization
Revised PIM section : corrected ATD pin mapping
Revised INT section : software interrupt priorities changed
Revised DBG section: NDB functionality, simultaneous arm and disarm
Revised SEC section : added disclaimer, corrected backdoor key text
Revised SPI section: typo ﬁxes only
Revised TIM section : removed redundant table, corrected bit name
Revised FTM section: Updated security description.