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FDC6302P - Digital FET/ Dual P-Channel

General Description

These Dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.

This very high density process is especially tailored to minimize on-state resistance.

Key Features

  • -25 V, -0.12 A continuous, -0.5 A Peak. R DS(ON) = 13 Ω @ VGS= -2.7 V R DS(ON) = 10 Ω @ VGS = -4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace multiple PNP digital transistors (IMHxA series) with one DMOS FET. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 4 3 5 2 6 1 Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ,TSTG ESD Parameter Drain-Source Volt.

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October 1997 FDC6302P Digital FET, Dual P-Channel General Description These Dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switchimg applications. Since bias resistors are not required this one P-Channel FET can replace several digital transistors with different bias resistors like the IMBxA series. Features -25 V, -0.12 A continuous, -0.5 A Peak. R DS(ON) = 13 Ω @ VGS= -2.7 V R DS(ON) = 10 Ω @ VGS = -4.5 V.