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CD4044BC - Quad 3-STATE NAND R/S Latches

Download the CD4044BC datasheet PDF. This datasheet also covers the CD4043BC variant, as both devices belong to the same quad 3-state nand r/s latches family and are provided as variant models within a single manufacturer datasheet.

Description

The CD4043BC are quad cross-couple 3-STATE CMOS NOR latches, and the CD4044BC are quad cross-couple 3STATE CMOS NAND latches.

Each latch has a separate Q output and individual SET and RESET inputs.

There is a common 3-STATE ENABLE input for all four latches.

Features

  • s Wide supply voltage range: 3V to 15V s Low power: 100 nW (typ. ) s High noise immunity: 0.45 VDD (typ. ) s Separate SET and RESET inputs for each latch s NOR and NAND configuration s 3-STATE output with common output enable Ap.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CD4043BC_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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CD4044BC Quad TRI-STATE NOR(NAND) R/S Latches National Semiconductor
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CD4044B CMOS QUAD 3-STATE R/S LATCHES Texas Instruments
CD4044BE CMOS QUAD 3-STATE R/S LATCHES Texas Instruments
CD4044BF CMOS QUAD 3-STATE R/S LATCHES Texas Instruments

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches October 1987 Revised January 1999 CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches General Description The CD4043BC are quad cross-couple 3-STATE CMOS NOR latches, and the CD4044BC are quad cross-couple 3STATE CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. There is a common 3-STATE ENABLE input for all four latches. A logic “1” on the ENABLE input connects the latch states to the Q outputs. A logic “0” on the ENABLE input disconnects the latch states from the Q outputs resulting in an open circuit condition on the Q output. The 3-STATE feature allows common bussing of the outputs.
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