74FR543 Datasheet | Fairchild Semiconductor

74FR543 Octal Latched Transceiver with 3-STATE Outputs January 1991 Revised August 1999 74FR543 Octal Latched Transceiver with 3-STATE Outputs General Description The 74FR543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Both the A and B outputs will source 15 m A and sink 64 m A. Features s Functionally equivalent to 74F543 s Back-to-back registers for storage s Bidirectional data path s A and B outputs have current sourcing capability of 15 m A and current sinking capability of 64 m A s Separate controls for data flow in each direction s Guaranteed pin-to-pin skew s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74FR543SC 74FR543SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram © 1999 Fairchild Semiconductor Corporation DS010902 .fairchildsemi. Pin Descriptions Pin Names OEAB, OEBA LEAB, LEBA CEAB, CEBA A0- A7 B0- B7 Description Output Enable Inputs Latch Enable Inputs Chip Enable Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs Functional Description The 74FR543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A-to-B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on (LEAB) input makes the A-to-B latches transparent; a subsequent LOWto-HIGH transition of the LEAB line puts the A latches...