M15T1G1664A - DDR3 SDRAM

Description

The 1Gb Double-Data-Rate-3(L), DDR3(L) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAM.

The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 bank devices.

and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages. DDR3(L) SDRAM Addressing Configuration M15T1G1664A # of Bank 8 Bank Address BA0.

ESMT

Part number	M15T1G1664A
Manufacturer	ESMT
File Size	7.20 MB
Description	DDR3 SDRAM
Datasheet	M15T1G1664A Datasheet
Additional preview pages of the M15T1G1664A datasheet.

Other Datasheets by ESMT

Click to expand full text

ESMT M15T1G1664A (2C) DDR3(L) SDRAM Feature  Interface and Power Supply  SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V)  SSTL_15: VDD/VDDQ = 1.5V(±0.

Published: Sep 20, 2018 |