Datasheet4U Logo Datasheet4U.com

74AUP2G34 - DUAL BUFFERS

Description

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.

The 74AUP2G34 is composed of two buffers with standard push-pull outputs designed for operation over a power supply range of 0.8V to 3.6V.

Features

  • Advanced Ultra Low Power (AUP) CMOS.
  • Supply Voltage Range from 0.8V to 3.6V.
  • ±4mA Output Drive at 3.0V.
  • Low Static Power Consumption.
  • ICC < 0.9µA.
  • Low Dynamic Power Consumption.
  • CPD = 6pF Typical at 3.6V.
  • Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for Slower Input Rise and Fall Time. The Hysteresis is Typically 250mV at VCC = 3.0V.
  • IOFF Supports Partial-Power-Down Mode Operation.
  • ESD Protection per JESD 22.
  • Exceeds 200-V.

📥 Download Datasheet

Datasheet preview – 74AUP2G34

📁 Similar Datasheet

  • 74AUP2G34 - Low-power dual buffer (NXP)
  • 74AUP2G34 - Low-power dual buffer (nexperia)
  • 74AUP2G3404 - Low-power buffer and inverter (nexperia)
  • 74AUP2G3407 - Low-power single buffer (nexperia)
  • 74AUP2G32 - Low-power Dual 2-input OR Gate (NXP)
  • 74AUP2G32 - Low-power dual 2-input OR gate (nexperia)
  • 74AUP2G38 - Low Power Dual 2-Input NAND Gate (NXP)
  • 74AUP2G38 - Low-power dual 2-input NAND gate (nexperia)
  • 74AUP2G00 - Low-power dual 2-input NAND gate (NXP)
  • 74AUP2G00 - Low-power dual 2-input NAND gate (nexperia)
Other Datasheets by Diodes

Full PDF Text Transcription

Click to expand full text
ADAVDAVANCNECDE ID INFNFORORMAMTAITIOONN 74AUP2G34 DUAL BUFFERS Description The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G34 is composed of two buffers with standard push-pull outputs designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. The gates perform the positive Boolean function: YA Features  Advanced Ultra Low Power (AUP) CMOS  Supply Voltage Range from 0.8V to 3.6V  ±4mA Output Drive at 3.0V  Low Static Power Consumption  ICC < 0.
Published: |