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74AHCT138T16 - 3 TO 8 LINE DECODER DEMULTIPLEXER

Download the 74AHCT138T16 datasheet PDF. This datasheet also covers the 74AHCT138 variant, as both devices belong to the same 3 to 8 line decoder demultiplexer family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74AHCT138 is an advanced high speed CMOS device that is designed to be pin compatable with 74LS low power Schottky types.

The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaining seven being high.

Key Features

  • Supply Voltage Range from 4.5V to 5.5V.
  • Sinks or Sources 8mA at VCC = 4.5V.
  • CMOS Low Power Consumption.
  • Schmitt Trigger Action at All Inputs.
  • Inputs Accept up to 6.0V.
  • ESD Protection Tested per JESD 22.
  • Exceeds 200-V Machine Model (A115-A).
  • Exceeds 2000-V Human Body Model (A114-A).
  • Exceeds 1000-V Charged Device Model (C101C).
  • Latch-Up Exceeds 250mA per JESD 78, Class II.
  • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2).
  • Halogen a.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHCT138-Diodes.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74AHCT138 3 TO 8 LINE DECODER DEMULTIPLEXER Description The 74AHCT138 is an advanced high speed CMOS device that is designed to be pin compatable with 74LS low power Schottky types. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaining seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3. The disabled device state results in all outputs being high. The enable state occurs with E1 and E2 asserted low and E3 asserted high. The multiple enable lines allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter.