74AHCT138 Datasheet 3-to-8 line decoder/demultiplexer

Manufacturer: Nexperia

Download the 74AHCT138 datasheet PDF. This datasheet also includes the 74AHC138 variant, as both parts are published together in a single manufacturer document.

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74AHCT138 3-to-8 line decoder/demultiplexer by Nexperia - Datasheet Preview — Note: The manufacturer provides a single datasheet file (74AHC138-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number	74AHCT138
Manufacturer	Nexperia
File Size	256.07 KB
Description	3-to-8 line decoder/demultiplexer
Download	74AHCT138 Download (PDF)

General Description

The 74AHC138;

74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard No.

Overview

74AHC138; 74AHCT138 3-to-8 line decoder/demultiplexer; inverting Rev.

5 — 10 September 2020 Product data sheet 1.

Key Features

Balanced propagation delays.
All inputs have Schmitt-trigger action.
Demultiplexing capability.
Multiple input enable for easy expansion.
Ideal for memory chip select decoding.
Inputs accepts voltages higher than VCC.
For 74AHC138 only: operates with CMOS input levels.
For 74AHCT138 only: operates with TTL input levels.
ESD protection:.
HBM JESD22-A114E exceeds 2000 V.
MM JESD22-A115-A exceeds 200.

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More Datasheets from Nexperia

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74AHCT138-Q100	3-to-8 line decoder/demultiplexer
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