CYRS1543AV18
Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 250 MHz clock for high bandwidth
- Four-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single multiplexed address input bus latches address inputs for read and write ports
- Separate port selects for depth expansion
- Synchronous internally self-timed writes
- QDR® II+ operates with 2.0 cycle read latency when the delay lock loop (DLL) is enabled
- Available in × 18, and × 36 configurations
- Full data coherency, providing most current data
- Core VDD = 1.8 (± 0.1 V); I/O VDDQ = 1.4 V to VDD
- Available in 165-ball CCGA (21 × 25 × 2.83 mm)
CYRS1543AV18 CYRS1545AV18
72-Mbit QDR® II+ SRAM Four-Word Burst Architecture with Rad Stop™...
